cpu [a0c1eb6c]
Tags: computers
1. TLBs
1. TLBs
- In normal multiprocessors, each CPU has it's own TLB, usually some split of small entries and big entries
2. Branch Predictions
2. Branch Predictions
3. SPARC [8f219dc8]
3. SPARC [8f219dc8]
4. Registers
4. Registers
- Nowadays, all registers can be used as general purpose registers
- RBP is used as a general purpose one, with RSP taking the role as a frame pointer. RIP is still in the stack memory region for each function call
info registersin gdb- Constants are encoded in instructions, but arbitrary values are retrieved from memory
- Goto is a
JMP - Function calls are
CALL - When a function is called from a caller, the callee needs to make room for local variables. In 64bit x86, usually the first six arguments are passed in registers
- Then it saves the base pointer into RBP, and then sets up the new base ptr
5. Cache Lines
5. Cache Lines
-
lore.kernel.org/netdev/20231129072756.3684495-2-lixiaoyan@google.com/
- Aligning structs in TCP gives a ton of improvements!
5.1. Types of Caches
5.1. Types of Caches
5.1.1. Direct Mapped Cache
5.1.1. Direct Mapped Cache
- Like consistent hashing, each memory address is used to map a block to a specific cache line
- both provide deterministic mapping
5.1.2. Fully Associative Cache
5.1.2. Fully Associative Cache
- Memory can be stored in any cache line, but we need to search to find it
5.1.3. Set Associative
5.1.3. Set Associative
- Memory address is used to determine the set, and the data can be placed in any block within the set
6. Load-Linked and Store-Conditional (LL/SC)
6. Load-Linked and Store-Conditional (LL/SC)
- Pair of instructions used in concurrent programming
- Achieves syncronization without locks
- Load-Linked - reads the current value from memory location and "links" it, typically by marking the address in a special way within the processor
- Store-Conditional - attempts to write a new value to the memory location that was read by LL. Write will only succeed if the location has not been udpated since LL was executed
7. Skylake
7. Skylake
-
www.youtube.com/watch?v=BVVNtG5dgks
- frontend
- Predecoder can do uOp fusion
-
Decoder "steering" can happen here, we need a decoder because we need to convert from crazy x86 instructions into uOps
-
Parallelism
-
- backend
- retire and post retire
